static time analysis vs dynamic time analysis

Static Time Analysis:

  This type of timing analysis checks the circuit timing requirement without the input / output data.
For a proper working design, both Static and dynamic timing analysis are necessary.

In a circuit there are certain parameters such as wire delay. register to register delay , ANd gate delay. XOR gate delay etc. In side the circuit for different paths , these values are added up for a particular path and compared with its maximum and minimum value .


Dynamic Timing Analysis:

Here different vectors of Input are given and outputs are verified in order to check the functionality of the circuit.This analysis is also used in asynchronous circuits and designs where multiple clocks are used.

Write a verilog code for 4 bit binary UP counter

module fourbit_upcount(Reset, Clock, E, Q);
  input Reset, Clock, E;
  output [3:0] Q;
  reg [3:0] Q;
  always @ (posedge Clock)
    if (!Reset)
      Q <= 0;
    else if (E)
      Q <= Q+1;
     
endmodule