some interview questions

1. Write a verily code for designing a FSM

2. draw schematic diagram for NAND and NOR gate (Transistor level)

3.difference between x and z ( that we see in simulation)

4.UVM block diagram

   uvm test - run_test 

  uvm env 

  uvm agents - driver , seqr , monitor  , 

driver talks to the DUT using the virtual interface 

5.UVM factory 

we can define the compenets in uvm factory . then we can override the objects 

 There are UVM macros that allow classes to be registered with the factory, and methods that allow certain types and instances of class objects to be overridden by its derived types.

set_type_overide_by_type

set_type_override_by_instance 

set_inst_override_by_type

set_inst_override_by_name 

6.virtual function

More questions about ASIC verification:

0. Count the number of 1 in a vector using System Verilog?
   Call $countones

1. Explain UVM agent

2. PERL file open close parse thru files

3. Give some example of system verily assertion

$countones : Returns the numbers of 1's in a bit vector. 
$past : Returns the values of the past. 
$stable : If the Signal is stable, then it returns 1. 
$isunknown : If th X is seen in expression , then it returns 1. 
$rose : returns true if the LSB of the expression changed to 1. Otherwise, it returns false. 
$fell : returns true if the LSB of the expression changed to 0. Otherwise, it returns false. 
$onehot : returns true if only 1 bit of the expression is high. 
$onehot0 : returns true if at most 1 bit of the expression is high.