More questions about ASIC verification:

0. Count the number of 1 in a vector using System Verilog?
   Call $countones

1. Explain UVM agent

2. PERL file open close parse thru files

3. Give some example of system verily assertion

$countones : Returns the numbers of 1's in a bit vector. 
$past : Returns the values of the past. 
$stable : If the Signal is stable, then it returns 1. 
$isunknown : If th X is seen in expression , then it returns 1. 
$rose : returns true if the LSB of the expression changed to 1. Otherwise, it returns false. 
$fell : returns true if the LSB of the expression changed to 0. Otherwise, it returns false. 
$onehot : returns true if only 1 bit of the expression is high. 
$onehot0 : returns true if at most 1 bit of the expression is high.