Write a system verilog assertion to check clock of 50 MHz

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module clk_check;

     timeunit 1ns;     

   timeprecision 100ps;  

realtime clk_period = 20.0/1.0ns; 

bit clk, RESET_N, ENABLE;

  property T_clk(real clk_period);

time current_time;

// disable iff(!RESET_N || !ENABLE)

(('1,current_time=$realtime) |=>

         (clk_period <= $realtime-(current_time-0.001ns))  &&

         (clk_period >= $realtime-(current_time + 0.001ns))); 

endproperty

 

assert_period:assert property (@(posedge clk)T_clk(clk_period))

$display("%t TB_INFO : clk  correct",$realtime); 

else

$warning("%t TB_INFO : clk not correct",$realtime);

initial forever #10 clk=!clk; 

initial begin 

$display("START CHECKING ");

repeat(10) @(posedge clk); 

// $display("%t %t TB_INFO : clk  correct",$realtime, $realtime);

$finish; 

end

   

endmodule : clk_check